1. Field of the Invention
The present invention relates to a solid-state imaging device, a method of manufacturing the same, and an electronic apparatus, such as a camera, including the solid-state imaging device.
2. Description of the Related Art
CMOS solid-state imaging devices are known as solid-state imaging devices. This CMOS solid-state imaging device is configured such that one pixel is formed by a photodiode and a plurality of pixel transistors, and a plurality of pixels is two-dimensionally arranged. This photodiode is a photoelectric conversion element that generates and accumulates signal charges in response to the amount of light received, and a plurality of pixel transistors is an element that transfers the signal charges from the photodiode, and reads out the signal charges as a signal. A plurality of pixel transistors can include, for example, four MOS transistors such as a transfer transistor, a reset transistor, an amplification transistor and a selection transistor. Alternatively, a plurality of pixel transistors can include three MOS transistors in which the selection transistor is omitted.
In the CMOS solid-state imaging device, from year to year, miniaturization of a unit pixel proceeds due to demand for increasing numbers of pixels, and thus it is difficult to miniaturize the pixel while holding the imaging characteristics such as the amount of saturated charges (for example, the amount of saturated electrons) Qs. That is, even when the area of the unit pixel is reduced, the area shared to the photodiode by the pixel transistor incapable of being miniaturized due to noise or process limitation lessens and the amount of saturated charges per unit area are not able to be maintained, which results in difficulty in miniaturizing the pixel. Consequently, a p-n junction for forming the photodiode is formed deeper inside of a semiconductor substrate than the pixel transistor and thus the overall area of the unit pixel is occupied by the photodiode. A CMOS solid-state imaging device is proposed in which the amount of saturated charges Qs is secured by this configuration, and charge transfer from the p-n junction deeper than the inside of the semiconductor substrate is realized by forming a vertical transfer transistor, so that miniaturization of the pixel is achieved (see Japanese Unexamined Patent Application Publication No. 2005-223084).
FIG. 22 shows a main cross-section structure of the pixel of such a CMOS solid-state imaging device. A CMOS solid-state imaging device 111 is a backside illumination type solid-state imaging device in which light illumination from the substrate backside is performed. In this CMOS solid-state imaging device 111, the pixel transistors included in each pixel, in this example, a transfer transistor Tr1, a reset transistor Tr2 and a amplification transistor Tr3 are formed in the surface side of the semiconductor substrate 112. A photodiode PD is formed in the lower portion of these pixel transistors. The photodiode PD includes, in the inside of the semiconductor substrate 112, an n-type semiconductor region 113 composed of a high impurity region (n+ region) 113A and a low impurity region (n region) 113B, serving as a charge accumulation region, and a p-type semiconductor region (p+ region) 114 having a high impurity concentration located at the surface side thereof.
The vertical transfer transistor Tr1 is configured to have a columnar transfer gate electrode 116 which is embedded within a longitudinal groove 110 reaching the inside of the n-type high concentration impurity region (n+ region) 113A of the photodiode PD in the depth direction from the surface of the semiconductor substrate 112 with a gate insulating film 115 interposed therebetween. An n-type source and drain region 117, serving as a floating diffusion (FD), is formed in the surface of the semiconductor substrate 112 so as to come into contact with the gate insulating film 115. The transfer gate electrode 116 of the vertical transfer transistor Tr1 is formed in a position equivalent to the center of a unit pixel 131, that is, the center of the photodiode PD. A p-type semiconductor region (p+ region) 121 having a high impurity concentration is formed so as to surround the gate insulating film 115 formed within the high impurity concentration region (n+ region) 113A of the photodiode PD.
The reset transistor Tr2 includes a pair of n-type source and drain regions 117 and 118 located at the surface side of the semiconductor substrate 112 and a reset gate electrode 123 formed with a gate insulating film interposed therebetween. The amplification transistor Tr3 includes a pair of n-type source and drain regions 119 and 120 located at the surface side of the semiconductor substrate 112 and a amplification gate electrode 124 formed with a gate insulating film interposed therebetween. A multilayer interconnection layer, in which a multilayered interconnections 126 are formed, is further formed on the semiconductor substrate 112 in which these pixel transistors (Tr1, Tr2, Tr3) are formed, with a interlayer insulating film 125 interposed therebetween. Although not shown in the drawing, a color filter and an on-chip microlens located at a position corresponding to each pixel on the color filter, and the like are further formed in the backside of the semiconductor substrate 112. In FIG. 22, reference numeral 130 indicates a pixel separation region. Reference numeral 131 indicates a unit pixel.